An efficient designed prototype technique for OFDM PAPR reduction using FPGA |
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| Authors: | W. Saad N. El‐Fishawy S. El‐Rabaie M. Shokair |
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| Affiliation: | Department of Electronic and Communication Engineering, Faculty of Electronic Engineering, Minoufiya University, Shibin el Kom, Egypt |
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| Abstract: | In this paper, a proposed designed technique to reduce OFDM peak‐to‐average power ratio (PAPR) value is performed. This designed technique contains a new block, which is inserted in the OFDM system. This proposed block is applied to the WiMAX system as an example of the OFDM technology. Afterwards, several MATLAB programs are executed to discuss the behavior and the characteristics of this proposed block. In addition, the effect of its insertion on the original system is studied. Because of this insertion, 0‐dB OFDM PAPR value can be achieved. Furthermore, it can be synthesized practically. This proposed system is implemented over a field‐programmable gate array (FPGA). The designed circuit is characterized by both its low complexity and its high speed. Moreover, it is a portable circuit. This means that it can be implemented over any FPGA kit regardless of its technology. Copyright © 2012 John Wiley & Sons, Ltd. |
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| Keywords: | OFDM PAPR FPGA VHDL |
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