Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.