| 基于PCI—E的北斗／GPS双模授时系统设计 |
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| 引用本文： | 杨会玲,唐,彬.基于PCI—E的北斗／GPS双模授时系统设计[J].苏州科技学院学报(工程技术版),2014(1):68-70,80. |
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| 作者姓名： | 杨会玲 唐 彬 |
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| 作者单位： | [1]苏州科技学院光电与信息技术研究所,江苏苏州215009 [2]安徽理工大学电气与信息工程学院,安徽淮南232001 |
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| 基金项目： | 江苏省青年科学基金项目（SBK201242850） |
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| 摘 要： | 针对时间同步装置与上位机通信接口等问题，结合北斗／GPs双模授时技术和PCIExpress总线技术，从应用角度出发，提出了一种新型的基于PCIE总线的北斗／GPS双模时间同步装置。利用数字可编程逻辑器件（FPGA）实现PCIE总线与北斗／GPS双模芯片之间的通讯和控制，通过PCIE总线驱动程序与上位机应用程序实现PCIE总线的授时信息实时交互。实验结果表明：系统设计方案可行、性能稳定可靠。
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| 关 键 词： | 北斗 GPS双模授时 FPGA PCIExpress |
Design of BD/GPS dual-mode system based on PCIE bus |
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| YANG Huiling,TANG Bin.Design of BD/GPS dual-mode system based on PCIE bus[J].Journal of University of Science and Technology of Suzhou：Engineering and Technology,2014(1):68-70,80. |
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| Authors: | YANG Huiling TANG Bin |
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| Affiliation: | 1.Opto-Electronic Information Technology Institute, SUST, Suzhou 215009, China; 2.College of Electrical and Information Engineering, Anhui University of Science and Technology, Huainan, 232001, China) |
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| Abstract: | As to the interface problems of time synchronization device and the computer communication, combining the theories of BD/GPS dual-mode technology with PCI Express bus technology, this paper puts forward a new kind of designed method of BD/GPS dual-mode system based on PCIE bus from the application point of view. The programmable gate array （FPGA） is used to realize the communication and control between the PCIE bus and BD/GPS dual-mode chip, and the real time interaction of the timing information of PCIE bus is realized by the driver of PCIE bus and the application code of computer. The result shows that the designed scheme is feasible and reliable. |
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| Keywords: | BD/GPS dual-mode FPGA PCI Express |
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