0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.

8 bit 250 MS/s Pipelined ADC with 60 dB SFDR in 0.13μm CMOS

A high speed and low power pipelined 8 bit 250 MS/s analog to digital converter (ADC) was described. To perform high speed operation with large effective input bandwidth, a track-and-hold amplifier (THA) was used in the front-end. To reduce the power consumption, the amplifiers in each stage were optimized and scaled in the following pipeline chain. At 250 MS/s conversion rate, the measurement results show that the total power consumption is 60 mW including on-chip clock generator, reference, voltage buffer, pipeline chain and digital logical with 1.2 V power supply. The proposed ADC achieves 60.1 dB SFDR, 46.6 dB SNDR and ENOB of 7.45 at 19 MHz input frequency. The effective resolution bandwidth is larger than 70 MHz. The ADC is designed using TSMC 0.13 μm 6-Metal 1-Poly CMOS process and occupies an area of 800 μm × 700 μm.