Double-frequency jitter figures in master–slave PLL networks

The main strategy used for distributing clock information in synchronous telecommunication networks is the master–slave. A particular node (master) provides the precise clock signals that are sent to the other nodes (slaves), which recover phase and frequency information by using phase-locked loops (PLLs). In spite of PLLs being equipped with low-pass filters, the recovered clock signals always contain second harmonic components that appear as a deterministic component of the whole phase jitter. Here, we study how the amplitude of this double-frequency jitter depends on the PLL parameters and delays. Chain and star topologies are considered with slave PLLs equipped with the most usual types of first-order low-pass filter. For both topologies, numerical simulations show that this kind of jitter depends on the position of the node in the chain or star being slightly dependent on the number of nodes.