| RS通信编码器的优化设计及FPGA实现 |
| |
| 引用本文： | 陈晨,徐伟,金光.RS通信编码器的优化设计及FPGA实现[J].现代电子技术,2010,33(17):88-90. |
| |
| 作者姓名： | 陈晨 徐伟 金光 |
| |
| 作者单位： | 1. 中国科学院,长春光学精密机械与物理研究所,吉林,长春,130033;中国科学院,研究生院,北京,100039
2. 中国科学院,长春光学精密机械与物理研究所,吉林,长春,130033 |
| |
| 摘 要： | RS码是纠错能力很强的一类线性纠错码类,被广泛用于各种通信系统和计算机存储系统中。介绍了一种优化编码生成多项式RS编码器的设计方法,用VHDL语言编写,利用ISE9.0软件仿真,烧写入FPGA,验证该RS编码方法正确。
|
| 关 键 词： | RS码 编码器 FPGA ISE |
Optimization Design of RS Communication Coder and Implementation of FPGA |
| |
| CHEN Chen,XU Wei,JIN Guang.Optimization Design of RS Communication Coder and Implementation of FPGA[J].Modern Electronic Technique,2010,33(17):88-90. |
| |
| Authors: | CHEN Chen XU Wei JIN Guang |
| |
| Affiliation: | 1. Changehun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences Changchun, Jilin 130033, China; 2. Graduate School, Chinese Academy of Sciences, Beijing 100039, China) |
| |
| Abstract: | RS code, which is widely used in various kinds of communication systems and computer storage systems, is a linear one with fine error-correcting capability. The method of designing RS coder with optimized code generator polynomials is described. It is written with VHDL and simulated with ISE 9.0. The result obtained by writing into FPGA is presented . The correctness and efficiency of this method is validated . |
| |
| Keywords: | FPGA ISE |
| 本文献已被 维普 万方数据 等数据库收录！ |
|
