Analog timing recovery for a noise-predictive decision-feedback equalizer |
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| Authors: | Keane J.P. Le M.Q. Hurst P.J. |
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| Affiliation: | Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA, USA; |
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| Abstract: | A timing recovery architecture and its CMOS implementation are described for a noise-predictive decision-feedback equalizer (NPDFE). The 0.5-/spl mu/m CMOS prototype includes timing recovery and the NPDFE and operates at 160 Mbit/s. The timing recovery blocks dissipate 27 mW from 3.3 V, occupy 0.2 mm/sup 2/, and achieve a root mean square jitter of 50 ps, which is 0.8% of a bit period. |
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