A depletion load self-aligned technology

Based on an accurate large signal MOSFET model, a computer aided design of the elementary NOR gate using a P channel depletion enhancement self-aligned technology has been done so as to minimize power-speed product. Threshold adjustment and gate self-registration are achieved by ion implantation. Measurements of main electrical and technological parameters are given. Computer aided design results are compared with measured performances on a 99 gates ring oscillator. For a 5 V supply voltage power-speed products as low as 1 pJ are obtained.