基于静态逻辑蕴涵的电路功耗优化

介绍一种针对经过工艺映射的组合逻辑电路进行功耗优化的方法.首先根据电路节点的翻转频率对节点进行分类,每次考虑一个节点,找出它在电路中的直接和间接蕴涵;然后利用这些蕴涵在电路添加一些逻辑门和连接,来增加电路的冗余;最后去除这些冗余来化简电路,去除那些高功耗的节点,从而减少整个电路的翻转活动,降低功耗.这个过程是重复的,每次重复从一个新的节点开始,最后得到一个跳变减少的电路.

Power Optimization of Technology-dependent Circuits Based on Static Logic Implications

This paper presents a method to the problem of optimizing technology mapped combinational circuits for low power. First, the nodes are sorted according to their switching activity, they are considered one at a time, and static logic implication is used to identify direct and indirect logic implications inside the network. These logic implications are exploited to add gates and connections to the circuit; this may help in eliminating high-power dissipating nodes, thus reducing the total switching activity and power dissipation of the entire circuit. The process is iterative; each iteration starts with a different target node. The end result is a circuit with a decreased switching power.