An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.