| A NEURAL NETWORK APPROACH TO GATE MATRIX LAYOUT |
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| 引用本文： | Zhou Qingshan Zou Yong Hu Jiandong(Dept. of Telecom. Engineering,Beijing University of Posts and Telecommunications,Beijing 100088). A NEURAL NETWORK APPROACH TO GATE MATRIX LAYOUT[J]. 电子科学学刊(英文版), 1997, 14(3): 209-214. DOI: 10.1007/s11767-997-1002-3 |
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| 作者姓名： | Zhou Qingshan Zou Yong Hu Jiandong(Dept. of Telecom. Engineering Beijing University of Posts and Telecommunications Beijing 100088) |
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| 作者单位： | Dept. of Telecom. Engineering，Beijing University of Posts and Telecommunications，Beijing 100088 |
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| 基金项目： | Support by Science Foundation of the Ministry of Posts and Telecommunications |
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| 摘 要： | Gate matrix layout problem plays an important role in integrated circuit design, but its optimization is NP-hard. In this paper, typical gate layout problem is analysed and adapted to neural network representation, furthermore the simulated results are given.
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A neural network approach to gate matrix layout |
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| Zhou Qingshan,Zou Yong,Hu Jiandong. A neural network approach to gate matrix layout[J]. Journal of Electronics, 1997, 14(3): 209-214. DOI: 10.1007/s11767-997-1002-3 |
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| Authors: | Zhou Qingshan Zou Yong Hu Jiandong |
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| Affiliation: | (1) Dept. of Telecom. Engineering, Beijing University of Posts and Telecommunications, 100088 Beijing |
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| Abstract: | Gate matrix layout problem plays an important role in integrated circuit design, but its optimization is NP-hard. In this paper, typical gate layout problem is analysed and adapted to neural network representation, furthermore the simulated results are given. |
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| Keywords: | Neural network Gate matrix Optimization |
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