| 3D透视校正纹理映射矩阵电路设计及实现 |
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| 引用本文： | 周珍艮,郭立.3D透视校正纹理映射矩阵电路设计及实现[J].电子技术应用,2007,33(12):48-50. |
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| 作者姓名： | 周珍艮 郭立 |
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| 作者单位： | 中国科学技术大学,电子科学与技术系,安徽,合肥,230026;铜陵学院,电气工程系,安徽,铜陵,244000;中国科学技术大学,电子科学与技术系,安徽,合肥,230026 |
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| 摘 要： | 3D图形硬件加速中,纹理映射属于像素处理阶段,透视校正中的纹理地址计算的特点是计算量大,且有实时性要求。本文设计了一个流水线脉动阵列结构来提高数据吞吐量。阵列的处理器单元(PE)为基于IEEE754单精度的32位浮点乘累加器,同时计算纹理坐标的除法电路也为单精度。
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| 关 键 词： | 脉动阵列 处理单元 纹理映射 FPGA |
| 修稿时间： | 2007年4月20日 |
Design and implementation of matrix circuit for 3D perspective correct texturing mapping |
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| ZHOU Zhen Gen,GUO Li.Design and implementation of matrix circuit for 3D perspective correct texturing mapping[J].Application of Electronic Technique,2007,33(12):48-50. |
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| Authors: | ZHOU Zhen Gen GUO Li |
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| Abstract: | In the 3D graphics hardware accelerators,the texture mapping is belong to pixels processing phase. Perspective-correct address calculation is generally intensive and real-time is requisite. In this paper,a pipeline systolic architecture is designed to improve pixel throughput. Processor elements(PE) are multiplication-add fused,accord with IEEE 754 single precision 32-bit floating point format. The single precision dividers are designed for texture coordinates calculation. |
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| Keywords: | systolic arrays PE texture mapping FPGA |
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