Behavioral modeling and simulation of fractional-N frequency synthesizer

A set of behavioral voltage-domain verilogA/verilog models is proposed in the paper, based on mathematical models of building blocks and some simulation strategies. The models include nonlinear effects of building blocks and can accurately predict the dynamic or stable characteristic of the closed loop. A three-order ΣΔ fractional-N PLL based frequency synthesizer with a 1.9 GHz central output frequency is implemented with the presented way. Cadence SpectreVerilog simulation results show that the behavioral modeling can provide a great speed-up over the transistor-level simulation. Correspondingly, the phase noise, spurious tones and loop locked time can also be accurately predicted, so it is helpful to optimization design based on system-level.