| 基于FPGA的FIR滤波器设计与仿真 |
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| 引用本文： | 宋承文,魏选平,刘浩淼.基于FPGA的FIR滤波器设计与仿真[J].电子技术,2011,38(4):49-51. |
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| 作者姓名： | 宋承文 魏选平 刘浩淼 |
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| 作者单位： | 第二炮兵工程学院; |
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| 摘 要： | FIR数字滤波器以其良好的线性相位特性被广泛使用,属于数字信号处理的基本模块之一.FPGA具有的灵活的可编程逻辑可以方便地实现高速数字信号处理.为了提高实时数字信号处理的速度,利用FPGA芯片内部的ROM实现一种查找表结构的FIR数字滤波器.并用MATLAB对实验结果进行仿真和分析,证明了设计的可行性.
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| 关 键 词： | 有限冲击响应滤波器 硬件描述语言 查找表 现场可编程门阵列 |
Design and Simulation of FIR Digital Filter Based on FPGA |
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| Song Chengwen,Wei Xuanping,Liu Haomiao.Design and Simulation of FIR Digital Filter Based on FPGA[J].Electronic Technology,2011,38(4):49-51. |
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| Authors: | Song Chengwen Wei Xuanping Liu Haomiao |
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| Affiliation: | Song Chengwen Wei Xuanping Liu Haomiao(The Second Artillery Engineering College,Xi'an) |
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| Abstract: | As a basic module for digital signal processing FIR digital filter is widely used in digital signal processing due to its good linear phase characteristics.FPGA has flexible programmable logic which can realize high speed digital processing conveniently.In order to improve the processing speed of real-time digital signal,the ROM inside of FPGA chip is utilized to implement a FIR digital filter with LUT(look-up-date) structure.The experimental results are simulated and analyzed based on MATLAB.It proves the ... |
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| Keywords: | FIR filter VHDL look up table(LUT) FPGA |
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