| 超宽带高速卷积译码器设计与实现 |
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| 引用本文： | 金英光,裴玉奎,葛宁,王有政.超宽带高速卷积译码器设计与实现[J].电子测量与仪器学报,2009,23(Z1):224-227. |
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| 作者姓名： | 金英光 裴玉奎 葛宁 王有政 |
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| 作者单位： | 清华大学信息科学技术学院电子工程系,北京,100084 |
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| 基金项目： | 国家高技术研究发展计划(863计划)，国家重点基础研究发展规划(973计划) |
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| 摘 要： | 超宽带系统卷积译码器在芯片实现中面临高速率、低功耗的挑战,本文在分析比较了多种Viterbi译码算法和结构的基础上,提出了一种适合芯片实现的并行回溯的译码器结构。该结构通过牺牲30%的存储资源以增加并行回溯分支,从而译码器工作时钟降至传统结构的一半。仿真和测试表明,该译码器在没有损失性能的情况下,单个译码模块速率可达到220Mbps,延时只有2.4μS,可支持低延时的突发模式。
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| 关 键 词： | 超宽带 译码器 并行回溯 |
Design and implementation of high speed convolution decoder for UWB |
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| Jin Yingguang,Pei Yukui,Ge Ning,Wang Youzheng.Design and implementation of high speed convolution decoder for UWB[J].Journal of Electronic Measurement and Instrument,2009,23(Z1):224-227. |
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| Authors: | Jin Yingguang Pei Yukui Ge Ning Wang Youzheng |
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| Affiliation: | Department of Electronic Engineering;School of Information Science and Technology;Tsinghua University;Beijing;100084 |
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| Abstract: | Chip design of convolution decoder for ultra-wide band(UWB) system is involved with two challenges-high speed and low power consumption.Based on the analysis of different algorithms and structures of viterbi decoding,an architecture of parallel trace-back decoder suitable for ASIC implementation is proposed.At the cost of 30%memory resource,this structure increases the number of the parallel trace-back branches,thus decreases frequency to half of the traditional one.Simulation and experiment results show th... |
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| Keywords: | UWB decoder parallel trace-back |
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