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Improved domino logic for high speed design |
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| Authors: | Song Jia Fei Liu Lijiu Ji |
| Affiliation: | Inst. of Microelectron., Peking Univ., Beijing, China; |
| Abstract: | Techniques are introduced to improve the speed of domino logic. With an inverted clock scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. HSPICE simulation shows that over 20% performance enhancement is achieved. |
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