通用处理器设计中硬件仿真验证

基于动态的RTL仿真依然是验证超大规模集成电路的主要方法。在使用动态仿真方法对通用微处理器这样大规模的设计进行功能验证时仿真速度成为了瓶颈，通常的解决方案是使用FPGA进行硬件的物理原型仿真，使用FPGA可以在较短的时间内测试大量的测试向量，但是使用FPGA物理原型验证的可调试很差。针对这一主要问题，提出了三级的层次化仿真验证环境，使用硬件仿真器的仿真加速作为中间层的解决方案，即可以提高仿真速度，也提供了良好的调试环境。同时针对大规模设计多片FPGA逻辑划分提出了改进的K—L算法，优化了FPGA的利用率和片间五连。

Hardware simulation for microprocessor verification

In microprocessor validation,dynamic simulation based verification is the dominant methodology.The speed of simulation became the bottleneck to verify the very large-scale designs such as general-purpose microprocessor.FPGA rapid prototyping system is anther efficient method; it can run millions of test vector in a short time. But it is very difficult to debug in FPGA system.This paper proposes to build two levels hardware simulation environment using emulator acceleration.The emulator not only accelerate the simulation,but also provide a powerful debug ability. Meanwhile the promotion K-L algorithm is introduced for logic partition of multi-FPGA system.This algorithm optimizes the utility and interconnect between FPGAs,and increases the performance of the FPGA prototyping system.