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SMAC: A VLSI Architecture for Scene Matching
Affiliation:1. Water Quality Centre, Trent University, 1600 West Bank Drive, Peterborough, ON K9J 7B8, Canada;2. Environmental Monitoring & Reporting Branch, Ontario Ministry of the Environment and Climate Change, 125 Resources Road, Toronto, ON M9P 3V6, Canada;1. Department of Biotechnology and Bioprocess Engineering, Faculty of Chemical and Process Engineering, Warsaw University of Technology, Waryńskiego 1, 00-645 Warsaw, Poland;2. Faculty of Material Science and Engineering, Warsaw University of Technology, Wołoska 141, 02-507 Warsaw, Poland
Abstract:Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. In this paper, we describe an efficient architecture for scene matching called SMAC (Scene Matching ArChitecture). The architecture achieves a significant amount of speedup by utilizing a large amount of parallelism and pipelining. Such an architecture can be used to compute the exhaustive search task of hierarchical scene matching, a technique used to reduce the amount of computations involved in scene matching applications. A prototype very large scale integration (VLSI) chip implementing a scaled down version of the proposed architecture has been designed and built. The prototype chip has been tested to be fully functional at a frequency of 50 MHz with a clock cycle of 20 ns. Based on the prototype design, it is estimated that the proposed architecture can process a 512 × 512 image with an 128 × 128 size template in about 15.36 μs, which corresponds to a rate of 65K frames per second.
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