三维芯片中TSV链式冗余修复电路的设计与实现

由于具有高集成度、高性能及低功耗等优点，三维芯片结构逐渐成为超大规模集成电路技术中的热门研究方向之一。TSV是三维芯片进行垂直互连的关键技术，然而在TSV的制作或晶圆的减薄和绑定过程中都可能产生TSV故障，这将导致与TSV互联的模块失效，甚至整个三维芯片失效。提出了一种基于TSV链式结构的单冗余/双冗余修复电路，利用芯片测试后产生的信号来控制该修复电路，将通过故障TSV的信号转移到相邻无故障的TSV中进行传输，以达到修复失效TSV的目的。实验结果表明，该电路结构功能正确，在面积开销较低的情况下，三维芯片的整体修复率可达91.97%以上。

Design and implementation of TSV chain redundancy repair circuit in 3D chip

The Three Dimensional (3D) chip structure is becoming one of the most popular academic research fields in VLSI owing to its advantages such as high integration density, high frequency, lower power, and so on. TSV is the key technology for vertical interconnections in 3D chips. However, TSVs may have some faults during the TSV fabrication or the process of wafer thinning and bonding, which causes that the modules related TSV lose efficacy, even the entire chip doesn’t work normally. A single redundancy and dual redundancy repair circuit based on TSV chain is proposed. The signals produced by chip testing are used to control repair circuit for the purpose of repairing the TSV defects and transferring the signals of fault TSV to the neighboring good TSV. The experimental results show that the function of this circuit structure is correct and the overall repair ratio can reach more than 91.97%, meanwhile the area overhead is lower.