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Some Properties of Division Factor Sequences in Fractional Phase Locked Loops
Authors:Thomas Musch  Burkhard Schiek
Affiliation:1. Ruhr-Universität Bochum, Institut für Hochfrequenztechnik, Universitätsstraße 150, D-44780 Bochum, Germany. Phone: +49(0)234/322 6496, Fax: +49(0)234/321 4167.;1. Tianjin Key Laboratory of Film Electronic and Communication Devices, School of Electrical and Electronic Engineering, Tianjin University of Technology, Tianjin 300191, China;2. RF Microelectronics Corporation, Tianjin, 300191, China;3. Electrical and Computer Engineering Department, Southern Illinois University Carbondale, 1230 Lincoln Drive, Carbondale, IL, 62901, USA;1. Advanced Technology Development Centre, IIT Kharagpur, 721302, India;2. Advanced VLSI Design Laboratory, IIT Kharagpur, 721302, India;3. Dept. of E&ECE, IIT Kharagpur, 721302, India;1. School of Microelectronics, Xidian University, Xi’an, Shaanxi 710071, China;2. School of Mechano-electronic Engineering, Xidian University, Xi’an 710071, China
Abstract:In the field of fractional divider phase-locked-loops (PLL) there exist several different methods for generating the division factor sequences controlling the programmable frequency divider in the PLL. The overall behaviour of the fractional PLL strongly depends on the proper choice of the division factor sequence. Therefore some concepts for generating these fractional sequences are discussed and the behaviour of the division factor sequences will be analysed with respect to the overall PLL behaviour. In addition some sources of disturbances are mentioned.
Keywords:Fractional-PLL   Frequency synthesis   Low phase noise
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