纯SV语言搭建验证平台

面对日益复杂的芯片系统设计和IP的高度集成方式,验证的重要性日益增加。传统的验证主要依赖于直接测试,虽然直接测试平台也可以采用有限的随机方式,但是通常是通过产生随机数的方式来实现的,而不是在每个数据单元简单地写入预先设定的值。直接测试方法适合于小设计,但一个典型SoC设计需要上千个测试用例,耗时太长。因此提升验证产量的唯一方法是减少产生测试所消耗时间。基于SystemVerilog具有丰富语言能力、能描述复杂验证环境、产生带约束的随机激励、面向对象编程、功能覆盖率统计等诸多优点,因此可以采用SystemVerilog语言功能构建一个验证平台。搭建验证环境时,可以应用带约束随机激励产生方法以及覆盖率驱动来提高验证效率,缩短验证周期,平台在queastasim上进行了仿真验证,并取得了比较好的结果。

Building of Verification Platform Using Pure SV Language

In the face of increasingly complex chip system design and a highly integrated approach to IP,verification is increasingly important.Traditional verification relies mainly on direct testing.Although direct test platforms can also use a limited random approach,they are usually implemented by generating random numbers instead of simply writing pre-set values in each data unit.Direct test methods are suitable for small designs,but a typical SoC design requires thousands of test cases and takes too long.Therefore,the only way to increase verification yield is to reduce the time it takes to generate a test.Based on the advantages of SystemVerilog,such as rich language ability,describing complex verification environment,generating constrained random excitation,object-oriented programming,function coverage statistics and so on,therefore,a verification platform can be built by the SystemVerilog language function.When constructing the verification environment,the constrained random excitation generation method and coverage drive can be applied to improve the verification efficiency and shorten the verification period.The platform is simulated and verified on queastasim,and ideal results are obtained.