首页 | 本学科首页   官方微博 | 高级检索  
     


Optimizing CAM-based instruction cache designs for low-power embedded systems
Authors:Juan L.   Alexander V.
Affiliation:aDepartment Ingenieria y Tecnología de Computadores, Universidad de Murcia, 30100 Murcia, Spain;bDepartment of Computer Science, University of California, Irvine, CA, USA
Abstract:Energy consumption and power dissipation are important concerns in the design of embedded systems and they will become even more crucial with finer process geometry, higher frequencies, deeper pipelines and wider issue designs. In particular, the instruction cache consumes more energy than any other processor module, especially with commonly used highly associative CAM-based implementations.Two energy-efficient approaches for highly associative CAM-based instruction cache designs are presented by means of using a segmented wordline and a predictor-based instruction fetch mechanism. The latter is based on the fact that not all instructions in a given I-cache fetch are used due to taken branches. The proposed Fetch Mask Predictor unit determines which instructions in a cache access will actually be used to avoid fetching any of the other instructions. Both proposed approaches are evaluated for an embedded 4-wide issue processor in 100 nm technology. Experimental results show average I-cache energy savings of 48% and overall processor energy savings of 19%.
Keywords:Embedded systems   Energy-efficient architectures   Fetch unit design
本文献已被 ScienceDirect 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号