Scheduling and variable binding for improved testability in high level synthesis |
| |
Authors: | AA Ismaeel R Mathew R Bhatnagar[Author vitae] |
| |
Affiliation: | Department of Electrical and Computer Engineering, College of Engineering and Petroleum, Kuwait University, P.O. Box 5969, Safat 13060, Kuwait |
| |
Abstract: | In this paper, we present a scheduling and a variable binding technique for improved testability in high level synthesis. The scheduling technique called cost based scheduling system (CBSS), is time constrained which minimizes the number of resources (operations) and the number of registers based on a cost function. The CBSS improves the life time of primary input and primary output variables, reduces the life times of intermediate variables and hence improves the controllability and observability. The testability of the register transfer level (RTL) structure generated by this schedule is therefore improved. CBSS considers all the variables and operations jointly for scheduling. CBSS supports various scheduling modes such as multicycled and chained operations, and pipelining. The complexity of our scheduling algorithm is O(c·n2) where c is the number of control steps and n is the number of operations to be scheduled. To generate a highly testable RTL structure, the CBSS is followed by a variable binding technique to bind the variables into registers. An integer linear programming (ILP) approach is proposed with an objective function that minimizes the number of registers and a set of constraints that improves the testability of the RTL structure. Various case studies are presented and the results on different benchmark examples show the potential of our approach. |
| |
Keywords: | Data flow graph Scheduling Binding Design for testability |
本文献已被 ScienceDirect 等数据库收录! |
|