基于高速缓存负荷均衡的动态二进制翻译研究

针对动态翻译时指令和数据高速缓存访问负荷大幅增加且增幅不均衡导致翻译器性能下降的问题，提出基于指令高速缓存与数据高速缓存访问负荷动态均衡的软硬件协同翻译方法.该方法为处理器设计高速缓存负荷平衡状态，该状态将数据高速缓存分为普通区和负荷平衡区(load balancing area, LBA)，普通区缓存正常的程序数据，负荷平衡区通过负荷转化通道(load transforming channel, LTC)吸收动态翻译器调度器地址空间转换操作在指令高速缓存上产生的部分负荷，以提高数据高速缓存利用率.EEMBC(embedded microprocessor benchmark consortium)测试基准实验结果表明，在同等处理器资源的情况下，该方法将指令高速缓存访问次数平均减少35%，数据高速缓存访问次数平均减少58%，动态翻译器综合性能提高171%.

Cache Load Balancing Oriented Dynamic Binary Translation

Based on the fact that the highly increasing load of instruction cache and data cache has led to great performance loss for DBT (dynamic binary translator), and the out-of-balance increasing rate between instruction cache and data cache makes the situation worse, this paper proposes a hardware-software-codesigned DBT acceleration mechanism that speeds up DBT performance by dynamically balancing load of instruction cache to data cache. The key idea of this mechanism is the design of the cache load balancing state for microprocessors. When microprocessor working in this state, the instruction cache stays the same as usual and the data cache is divided into two areas: normal-accessing-area and load-balancing-area. The normal-accessing-area caches regular program data just as the traditional data cache does. However, the load-balancing-area is quite different. It doesn’t cache regular program data, but supports load-transforming-channel, which is used to transform and assimilate most of the instruction cache load caused by scheduler of the DBT. Main work of the scheduler is converting jump target address from source machine code space to target machine code space. Experimental results based on EEMBC(embedded microprocessor benchmark consortium) benchmarks show that the access load of instruction cache is reduced by 35%, data cache is reduced by 58%, and overall performance of the QEMU(quick emulator) DBT is improved by 171%.