The dangers of simplistic delay models |
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Authors: | David M Wessels Jon C Muzio |
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Affiliation: | (1) Department of Computer Science, James Cook University of North Queensland, QLD 4811 Townsville, Australia;(2) VLSI Design and Test Group, Department of Computer Science, University of Victoria, P.O. Box 3055, V8W 3P6 Victoria, B.C., Canada |
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Abstract: | The identification of sensitizable paths and the determination of path delays play key roles in many delay fault testing schemes. In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits. We provide recommendations on the minimum acceptable model for identifying critical paths, and a minimum acceptable model for determining maximum circuit delays. In particular, we recommend against the use of delay models which fail to distinguish between rise and fall delays. Such models, including the commonly-used unit-delay model, are shown to significantly misrepresent circuit delay behaviour, particularly with respect to critical paths and long false paths.This research is supported by the Natural Sciences and Engineering Research Council of Canada. |
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Keywords: | Delay models circuit delays critical paths path sensitization |
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