An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET |
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| Authors: | Harsupreet Kaur R.S. Gupta |
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| Affiliation: | a Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi 110 021, India
b Department of Physics, Motilal Nehru College, New Delhi 110 021, India |
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| Abstract: | In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L1/L2 ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement. |
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| Keywords: | Device modeling Surrounding gate MOSFET Graded channel Drain current enhancement Reduced drain conductance Improved breakdown voltage |
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