一种基于寄存器翻转时刻随机化的抗DPA攻击技术

在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的随机变化.针对跨时钟域的数据和控制信号,提出了需要满足的时序约束条件的计算方法,同时还分析了不同时钟频率对寄存器翻转时刻随机化程度的影响.以AES密码算法协处理器为例,实现了所提出的寄存器翻转时刻随机化技术,通过实验模拟的方法验证了理论分析的正确性.实验结果显示,在合理选择电路工作时钟频率的情况下,所提出的技术能够有效提高密码算法电路的抗DPA攻击性能.

A DPA Resistant Technology Based on Register Switching Time Randomization

Differential power analysis(DPA) attack is one of the most effective side channel attack technologies against the security chip.The success of DPA attack depends on two aspects:one is the correlation between power consumption and data,and the other is the synchronization of target function signals.Countermeasures based on power balanced logic styles aim to eliminate the power dependence.However,these methods introduce large performance,power,and area cost.Another effective way to counteract DPA attack is making the target function signals asynchronous.As the output signals of registers are always chosen as target function,the asynchronism can be achieved by randomizing the register switching time.The resistibility of register switching time randomization against DPA attack is analyzed theoretically at first.Then a novel countermeasure based on this idea is presented.The switching time of critical registers are randomized by the phase difference of different clock domains.The computing method of timing constraints to data and control signals transferred between the different clock domains is introduced.And the effect of clock frequencies on the randomization is analyzed.This countermeasure is implemented in an AES coprocessor,and the simulation experiment proves the correctness of the theoretical analysis.The simulation results show that this technology can improve the preventing ability of the cryptographic circuit under the special working clock frequency.