| SEC中的全数字锁相环的分析及设计 |
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| 引用本文： | 张继勇,王爱国. SEC中的全数字锁相环的分析及设计[J]. 光通信研究, 2006, 32(6): 22-23,41 |
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| 作者姓名： | 张继勇 王爱国 |
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| 作者单位： | 1. 武汉邮电科学研究院,湖北,武汉,430074
2. 烽火通信科技股份有限公司,湖北,武汉,430074 |
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| 摘 要： | 文章首先介绍了全数字锁相环(ADPLL)的基本结构和工作原理,并进行了数学建模,计算了其主要的参数指标;然后,针对SDH设备时钟(SEC)设计了一种切实可行的低抖动ADPLL的电路结构,并对其各个组成部分进行了具体的电路分析和设计,通过微机适当配置,可以使该设计的结果得到优化;最后,通过现场可编程门阵列(FPGA)验证,给出了测试结果.
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| 关 键 词： | 全数字锁相环 数控振荡器 分频器 抖动 |
| 文章编号： | 1005-8788（2006）06-0022-02 |
| 收稿时间： | 2006-05-23 |
| 修稿时间： | 2006-05-23 |
Analysis and design of all digital phase-locked loops in SEC |
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| Zhang Jiyong,Wang Aiguo. Analysis and design of all digital phase-locked loops in SEC[J]. Study on Optical Communications, 2006, 32(6): 22-23,41 |
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| Authors: | Zhang Jiyong Wang Aiguo |
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| Affiliation: | 1. Wuhan Research Institute of Post and Telecommunications, Wuhan 430074, China; 2. FiberHome Telecommunication Technologies Co. , Ltd. , Wuhan 430074, China |
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| Abstract: | In this paper,the basic structure and operating principle of ADPLL(All Digital Phase-Locked Loop) are first introduced,which is followed by the analyses of its mathematic model and the calculation of its main parameters.Then,a feasible low-jitter ADPLL circuit structure for SEC(SDH equipment clock)is designed and specific circuit analysis of and designs for each part of ADPLL made,which is optimized by appropriate CPU configurations.Finally,this circuit is verified by FPGA and the test result given. |
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| Keywords: | ADPLL Digital-Controlled Oscillator(DCO) divider jitter |
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