有效的模(2n+1)乘算法及其VLSI设计

模乘运算在剩余数值系统、数字信号处理系统及其它领域都具有广泛的应用,模乘法器的硬件实现具有重要的作用。提出了一种改进的模(2~n 1)余数乘法器的算法及其硬件结构,其输入为通常的二进制表示,因此无需另外的输人数据转换电路而可直接用于数字信号处理应用。通过利用模(2~n 1)运算的周期性简化其乘积项并重组求和项,以及采用改进的进位存储加法器和超前进位加法器优化结构以减少路径延时和硬件复杂度。比较其它同类设计,新的结构具有较好的面积、延时性能。

Efficient Algorithm and VLSI Architecture for Module (2n +1) Multiplier

Hardware implementation of modulo multipliers is a very important task because modulo multiplication is widely used in residue number system (RNS)arithmetic,digital signal processing (DSP)and other applications.In this paper,an efficient algorithm and architecture for modulo(2~n 1)multiplier was presented,which were based on the modified carry save adder(MCSA) array and the modified carry look-ahead adder(MCLA).Where the input operands are represented as normal binary,resulting in no need of additional conversion circuit for DSP applications.The path delay and hardware complexity are reduced considerately by making use of periodicity of modulo(2~n 1)operation to simplify production terms and re-combining the summation terms.Compared with the other designs,the proposed architecture is simple and efficient with regard to area and delay.