DFT for delay fault testing of high-performance digital circuits |
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Authors: | Bhaskar Chatterjee Manoj Sachdev Keshavarzi A |
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Affiliation: | Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada; |
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Abstract: | Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads. |
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