A Low Power SRAM/SOI Memory Cell Design

提出一种改进4管自体偏压结构SRAM/SOI单元. 基于TSUPREM4和MEDICI软件的模拟和结构性能的分析，设计单元结构并选取结构参数. 该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOS SRAM单元中的pMOS元件，具有面积小、工艺简单的优点. 该结构可以在0.5V的电源电压下正常工作，与6管单元相比，该单元瞬态响应正常，功耗只有6管单元的1/10，满足低压低功耗的要求.

A Low Power SRAM/SOI Memory Cell Design

A modified four transistor (4T) self-body-bias structured SRAM/SOI memory cell is proposed.The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p+ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM.Furthermore,this structure can operate safely with a 0.5V supply voltage,which may be prevalent in the near future.Finally,compared to conventional 6T CMOS SRAM,this structure's transient responses are normal and its power dissipation is 10 times smaller.