Thermal Stress Assessment for Transient Liquid-Phase Bonded Si Chips in High-Power Modules Using Experimental and Numerical Methods

The potential of transient liquid-phase (TLP) bonding for chip packaging applications has been evaluated, focusing on three interlayer arrangements (Ag-Sn-Ag, Ni-Sn-Ni, and Ag-Sn-Ni). Shear tests on TLP-bonded components provided the interlayer-dependent mechanical strength as well as failure mode and position. Critical local stresses, i.e., failure criteria, within the intermetallic compound (IMC) layer were derived by replicating the shear test conditions with finite-element methods. The missing coefficient of thermal expansion for Ag₃Sn IMC was obtained by producing small IMC bulk samples and subjecting them to dilatometric measurements. The experimental results were implemented into a finite-element model of a representative power module architecture to provide first predictions on thermally induced residual stresses that could be classified into fail/safe, as successfully validated by TLP chip bonding experiments. A numerical parameter study then assessed thermal stresses, including failure prediction and design optimization for TLP-bonded Si chips, considering the influence of process temperature, service conditions, TLP interlayer system, and metallization layers within the TLP joint. The presented procedure serves as a guideline to choose an appropriate TLP interlayer system for predefined boundary conditions, or vice versa.