| Abstract: | A suitable large signal design method of distributed power amplifiers, based on the optimum FET load requirement for high power operation, is proposed in this article. The gate and drain line characteristic admittances are determined, providing both the initial values and right directions for an optimum design. To validate the proposed design method, a FET amplifier demonstrator with a gate periphery of 1.2 mm has been manufactured at the Texas Instruments foundry. The MMIC distributed amplifier demonstrated an improved power density performance of 340 mW/mm over the 2–18-GHz frequency band associated with a minimum of 13% power-added efficiency and 24% drain efficiency at 1-dB compression in CW operation. © 1996 John Wiley & Sons, Inc. |
