| Abstract: | It is the time to explore the fundamentals ofI DDT testing when extensive work has been done forI DDT testing since it was proposed. This paper precisely defines the concept of average transient current (I DDT) of CMOS digital ICs, and experimentally analyzes the feasibility ofI DDT test generation at gate level. Based on the SPICE simulation results, the paper suggests a formula to calculateI DDT by means of counting only logical up-transitions, which enablesI DDT test generation at logic level. The Bayesian optimization algorithm is utilized forI DDT test generation. Experimental results show that about 25% stuck-open faults are withI DDT test generation. 2.5, and likely to beI DDT testable. It is also found that mostI DDT testable faults are located near the primary inputs of a circuit under test.I DDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation. Furthermore, some redundant stuck-at faults can be detected by usingI DDT testing. |
