基于保护门的纳米CMOS电路抗单粒子瞬态加固技术研究

随着器件特征尺寸的缩减,单粒子瞬态效应(SET)成为空间辐射环境中先进集成电路可靠性的主要威胁之一。基于保护门,提出了一种抗SET的加固单元。该加固单元不仅可以过滤组合逻辑电路传播的SET脉冲,而且因逻辑门的电气遮掩效应和电气隔离,可对SET脉冲产生衰减作用,进而减弱到达时序电路的SET脉冲。在45 nm工艺节点下,开展了电路的随机SET故障注入仿真分析。结果表明,与其他加固单元相比,所提出的加固单元的功耗时延积(PDP)尽管平均增加了17.42%,但容忍SET的最大脉冲宽度平均提高了113.65%,且时延平均降低了38.24%。

Study on Hardened Technique to Single Event Transient in Nano-Meter CMOS Circuits Based on Guard Gate

As the feature size of the device scales down, single event transient (SET) has become one of the most important threat to the reliability of advanced integrated circuits (ICs) in space radiation environment. A hardened SET cell was proposed based on the guard gate. The proposed cell could not only filtrate the SET pulse propagated from the combinational logic circuits, but also reduce the strength of SET pulse due to the electrical masking effect and electrical isolation. Then the SET arrived at the sequential circuits was attenuated. The analysis for random SET fault injection at 45 nm process node was performed. The results show that compared with other hardened SET cells, although the power delay product (PDP) overhead of the proposed cell is increased by an average of 17.42%, the maximum pulse width of the tolerant SET is improved by an average of 113.65%, and its delay is reduced by an average of 38.24%.