延迟优化的统一可编程互连电路设计和实现

本文设计了一种对可编程逻辑单元CLB和可编程输出单元IOB均具有统一结构的可编程互连电路。通过偏移互连线和回线技术，使得同种可编程互连线的负载分布均匀，保证了可编程逻辑器件FPGA芯片中信号传输的可预测性和规整性；同时，设计过程中对编程点和驱动器电路进行专门的优化设计，减少了5%延时。运用该互连电路到实例FPGA芯片--FDP芯片中，流片后实测数据表明：该可编程互连电路中各种互连线功能正确，可以正确地完成各种信号的互连，整个芯片的延迟统一而且可预测。

Designand implementation of a delay-optimized universal programmable routing circuit for FPGAs

This paper presents a universal field programmable gate array(FPGA) programmable routing circuit,focusing primarily on a delay optimization.Under the precondition of the routing resource's flexibility and routabil-ity,the number of programmable interconnect points(PIP) is reduced,and a multiplexer(MUX) plus a BUFFER structure is adopted as the programmable switch.Also,the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circu...