| 三维TPC译码器的设计及FPGA实现 |
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| 引用本文： | 瞿海惠,张浩,杨亚光,龙飞.三维TPC译码器的设计及FPGA实现[J].现代电子技术,2013(23):26-29. |
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| 作者姓名： | 瞿海惠 张浩 杨亚光 龙飞 |
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| 作者单位： | 中国科学院微电子研究所,北京100029 |
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| 基金项目： | 国家科技重大专项：面向行业专网应用的带宽可变频点可变无线宽带射频芯片研发（Y2GZ316001） |
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| 摘 要： | Turbo乘积码（TPC）是一种性能优秀的纠错编码方法，它具有译码复杂度低、译码延时小等优点，且在低信噪比下可以获得近似最优的性能。介绍了基于Chase算法的三维TPC软输入软输出（SISO）迭代译码算法，提出了三维TPC译码器硬件设计方案并在FPGA芯片上进行了仿真和验证。测试结果表明，该译码器具有较高的纠错能力，满足移动通信误码率的要求。
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| 关 键 词： | 三维TPC Chase算法 软输入软输出 FPGA实现 |
Design and FPGA realization of 3-D TPC decoder |
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| QU Hai-hui,ZHANG Hao,YANG Ya-guang,LONG Fei.Design and FPGA realization of 3-D TPC decoder[J].Modern Electronic Technique,2013(23):26-29. |
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| Authors: | QU Hai-hui ZHANG Hao YANG Ya-guang LONG Fei |
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| Affiliation: | (Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China) |
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| Abstract: | Turbo product code （TPC） is a kind of forward error correction code （FEC）with excellent performance. TPC has the advantages of low decoding complexity and short decoding delay, and can achieve near-optimum performance at low signal-to- noise ratio. The soft-in soft-out（SISO）iterative decoding method for three-dimensional（3D）TPC based on Chase algorithm is intro- duced. The hardware design scheme of 3-D TPC decoder is proposed and verified on FPGA platform. The simulation results show that the decoder has high error-correcting capability and meets the requirement of mobile communication on bit error rate. |
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| Keywords: | 3-D TPC Chase algorithm SISO FPGA realization |
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