Border-Trap Characterization in High-κ Strained-Si MOSFETs |
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| Authors: | Debabrata Maji Duttagupta SP Rao VR Chia Ching Yeo Byung-Jin Cho |
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| Affiliation: | Indian Inst. of Technol., Bombay; |
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| Abstract: | In this letter, we focus on the border-trap characterization of TaN/HfO2/Si and TaN/HfO2/strained-Si/Si0.8Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si0.8Ge0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed. |
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