| 6加数并行加法器及扩展接口的研究 |
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| 引用本文： | 刘杰,易茂祥. 6加数并行加法器及扩展接口的研究[J]. 微电子学与计算机, 2009, 26(12) |
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| 作者姓名： | 刘杰 易茂祥 |
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| 作者单位： | 1. 阜阳师范学院,物理与电子科学学院,安徽,阜阳,236041
2. 合肥工业大学,应用物理系,安徽,合肥,230009 |
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| 基金项目： | 安徽省高校省级自然科学研究资金项目 |
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| 摘 要： | 提出了一种6个加数的并行加法器及其接口扩展的研究方案.论述了所提新型加法器的工作原理和过程,同时描述了接口扩充思想.最后,采用MAX+PLUSⅡ对设计电路进行了模拟验证.实验结果说明了所提加法器的设计合理性,也证明了该加法器对6个加数的计算比采用串行累加更快.
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| 关 键 词： | 算术逻辑运算单元 加法器 超前进位加法器 |
Research on a Parallel Adder with 6 Binary Addends and Its Interface |
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| LIU Jie,YI Mao-xiang. Research on a Parallel Adder with 6 Binary Addends and Its Interface[J]. Microelectronics & Computer, 2009, 26(12) |
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| Authors: | LIU Jie YI Mao-xiang |
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| Abstract: | A parallel adder with 6 binary addends and its interface are proposed. Working principle and process of the novel adder are discussed, and its interface extension is described. Finally, MAX+ PLUS II is exploited to simulate and validate the proposed adder. Experimental results indicate that the proposed design scheme is not only reasonable, but also can faster calculate 6 binary addends than a carry look-ahead adder using the serial adding scheme. |
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| Keywords: | arithmetic logic unit adder carry look-ahead adder |
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