High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip |
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Authors: | G A Ruiz J A Michell and A Burón |
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Affiliation: | (1) Departamento de Electrónica y Computadores, Facultad de Ciencias, Universidad de Cantabria, Avda. de Los Castros s/n, 39005 Santander, Spain |
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Abstract: | This paper presents a 2-D DCT/IDCT processor chip for high data rate image processing and video coding. It uses a fully pipelined
row–column decomposition method based on two 1-D DCT processors and a transpose buffer based on D-type flip-flops with a double
serial input/output data-flow. The proposed architecture allows the main processing elements and arithmetic units to operate
in parallel at half the frequency of the data input rate. The main characteristics are: high throughput, parallel processing,
reduced internal storage, and maximum efficiency in computational elements. The processor has been implemented using standard
cell design methodology in 0.35 μm CMOS technology. It measures 6.25 mm2 (the core is 3 mm2) and contains a total of 11.7 k gates. The maximum frequency is 300 MHz with a latency of 172 cycles for 2-D DCT and 178
cycles for 2-D IDCT. The computing time of a block is close to 580 ns. It has been designed to meets the demands of IEEE Std.
1,180–1,990 used in different video codecs. The good performance in the computing speed and hardware cost indicate that this
processor is suitable for HDTV applications.
This work was supported by the Spanish Ministry of Science and Technology (TIC2000-1289).
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Keywords: | discrete cosine transform (DCT) inverse discrete cosine transform (IDCT) image compression row column decomposition parallel pipelined architectures very large scale integration (VLSI) |
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