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Design for Stability of High-Speed Integrated Photoreceivers: A Tutorial
Authors:Email author" target="_blank">André?BoyoguénoEmail author  Mohamad?Sawan  Mustapha?Slamani
Affiliation:(1) Department of Electrical Engineering, Ecole Polytechnique de Montréal, P.O. Box 6079, Station Centre-Ville, Montréal, Québec, H3C 3A7, Canada;(2) IBM, Test Development Group, 1000 River Street, Mail Stop 862G, VT, 05452
Abstract:We propose a Design for Stability (DFS) methodology dedicated to the design of reliable high-speed integrated photoreceiver front-ends. This methodology based on the stability factor, S-parameters and Z-parameters analysis is made of four rules that high-speed designers will apply during the stability check of their design. To demonstrate its effectiveness, the proposed DFS methodology was applied to build a transimpedance amplifier (TIA) compliant to Synchronous Optical Network (SONET) OC-192 (10-Gb/s) standard. Experimental results in agreement with initial design specifications show excellent performances such as: 11 GHz bandwidth, −20 dBm sensitivity measured at 10-Gb/s for a Bit Error Rate (BER) of 10− 9 and 10 ps peak-to-peak jitter.
Keywords:design for stability  design methodology  transimpedance amplifier  S-parameters
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