ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战、文章分析了时钟偏移的产生机理,然后提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,最后还分析了如何利用有用的时钟偏移来改善电路的时序。

Analysis of Clock Skew in ASIC Design

Clock skew becomes more and more important to synchronization circuits in current ASIC design and it is an increasing concern for high-speed circuit designers. Therefor, it has been a tough challenge to reduce defect of clock skew in designs. In this paper firstly the generation principle of clock skew is analyzed and then for solving its disadvantage we propose a approach that we insert diversified buffers in clock trees in order to balance the clock network. Finally, we analyze how to fix the timing violation of our designs by using useful clock skew.