| 基于FPGA的异步LVDS过采样的研究和实现 |
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| 引用本文： | 母方欣,李大鹏. 基于FPGA的异步LVDS过采样的研究和实现[J]. 电子技术, 2014, 0(7): 42-45 |
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| 作者姓名： | 母方欣 李大鹏 |
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| 作者单位： | 西安航空计算技术研究所 |
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| 摘 要： | 针对LVDS接口,研究并实现了一种基于FPGA的LVDS过采样技术,重点对LVDS过采样技术中系统组成、ISERDESE2、时钟采样、数据恢复单元、时钟同步状态机等关键技术进行了描述,并基于Xilinx FPGA进行了验证,传输速率达到了1.25Gbps。文章的研究为基于FPGA实现系统之间的高速互连具有一定的工程参考价值。
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| 关 键 词： | 低电压差分信号传输 过采样 时钟恢复单元 |
Research and Implementation of Asynchronous LVDS Oversampling Based on FPGA |
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| Mu Fangxin,Li Dapeng. Research and Implementation of Asynchronous LVDS Oversampling Based on FPGA[J]. Electronic Technology, 2014, 0(7): 42-45 |
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| Authors: | Mu Fangxin Li Dapeng |
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| Affiliation: | (AVIC Xi＇an Aeronautics Computing Technique Research Institute) |
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| Abstract: | Aiming at LVDS interface this paper research and implement a kind of asynchronous LVDS oversampling technology based on FPGA. The paper describes the key technologies in the LVDS oversampling, including system composition, ISERDESE2, clock sampling, data recovery unit and clock align machine in detail. And it validates the validity of the system based on Xilinx FPGA, the transmission speed achieved 1.25Gbps. This paper is of certain engineering reference value for high speed interconnection between systems based on FPGA. |
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| Keywords: | LVDS oversampling data recovery unit |
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