非线性优化的时间数字转换器设计

在由FPGA超前进位单元级联构成的抽头延时链中,非线性通常较差,是TDC测量系统需要解决的重要问题之一。为了解决该问题,文章在已有的抽头采样序列(“SCSC”)基础上,提出了“混合”抽头采样序列的方法,显著改善了延时单元的非均匀性。所搭建的TDC包含了抽头延时链、采样逻辑电路、编码逻辑电路、码密度校准等模块,并在Xilinx Kintex-7系列芯片上进行验证。测试结果表明,提出的方法相较于“SCSC”序列下的微分非线性降低了32.0%,积分非线性降低了22.8%。通过进一步校准,所实现的TDC分辨率(LSB)为13.51 ps,测量精度为19.17 ps,微分非线性为-0.45, 0.96] LSB,积分非线性在-3.27, 1.33] LSB之间。

Design of a Nonlinear Optimized Time to Digital Converter

The poor nonlinearity of the tapped delay chain cascaded by Carry4 units in FPGA is one of the important problems to be solved in TDC measurement system. Based on the existing tapped sampling sequence (" SCSC "), a method of "mixed" tapped sampling sequence was proposed to solve this problem, and the non-uniformity of delay units was significantly improved. The built TDC consisted of modules such as tapped delay chain, sampling and coding logic circuit, and code density calibration, and was verified on a Xilinx Kintex-7 series chip. The experimental results show that the differential nonlinearity of this method is reduced by 32.0% and the integral nonlinearity is reduced by 22.8% compared with that of the "SCSC" sequence. Through further calibration, the achieved resolution (LSB) of TDC is 13.51 ps, the measurement accuracy is 19.17 ps, the differential nonlinearity range is -0.45,0.96] LSB, and the integral nonlinearity range is -3.27,1.33] LSB.