一种基于斜率-电阻相位插值的低功耗十倍频电路

基于65 nm CMOS工艺设计了一种低功耗低成本十倍频电路。在1.2 V电源电压下，电路功耗小于0.53 mW。提出了一种低复杂度的5段斜率-电阻相位插值方法，通过对四路正交斜率信号进行电阻相位插值，在8 MHz到24 MHz的输入频率范围内，实现了可重构的十倍频电路。该电路结构简单，仅包含正交方波信号发生器、斜坡信号发生器和提出的5段斜率-电阻相位插值器，可用于低功耗、低成本的倍频场合，且具有可接受的频率偏差。在输入频率为16 MHz,输入功率为-2.0 dBm时，电路输出功率为-12.9 dBm,倍频效率为4.40%。

A Low Power 10-Fold Frequency Multiplier Based on Slope-Resistance Phase Interpolation Scheme

A low power and low cost 10-fold frequency multiplier was designed in a 65-nm CMOS process. The power consumption was less than 0.53 mW from a 1.2-V supply voltage. A 5-segment slope-resistance phase interpolation scheme was proposed with low complexity. By performing resistance interpolation on four-path orthogonal slope signals, a reconfigurable 10-fold frequency structure was achieved within the input frequency range from 8 MHz to 24 MHz. The circuit was simple and only included a quadrature square-waveform generator, a slope-waveform generator and the proposed 5-segment slope-resistance phase interpolators, which could be used in low power, low cost frequency doubling cases, with an acceptable frequency deviation. The proposed circuit achieves an output power of -12.9 dBm with an input power of -2.0 dBm at the input frequency of 16 MHz, and obtains a frequency multiplication efficiency of 4.40%.