| 基于FPGA的数字脉冲压缩系统实现 |
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| 引用本文： | 庞龙,陈禾. 基于FPGA的数字脉冲压缩系统实现[J]. 现代电子技术, 2010, 33(14): 190-192,195 |
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| 作者姓名： | 庞龙 陈禾 |
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| 作者单位： | 北京理工大学,信息与电子学院,雷达技术研究所,北京,100081 |
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| 摘 要： | 针对采用线性调频信号的宽带雷达系统,完成单通道高速数据采集和数字脉冲压缩系统的工程实现。系统使用ADS5500完成14位6、0 MSPS的数据采集,使用FPGA实现1 024点的数字脉冲压缩。脉冲压缩模块采用快速傅里叶变换IP核进行设计,可以在脉冲压缩的不同阶段对其进行复用,分别完成FFT和IFFT运算,从而使硬件规模大大减少。系统采用块浮点数据格式以提高动态范围,同时减小截断（或舍入）误差对输出信噪比的影响。
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| 关 键 词： | 数字脉冲压缩 快速傅里叶变换 块浮点 知识产权核 现场可编程门阵列 |
Implementation of Digital Pulse Compression System Based on FPGA |
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| PANG Long,CHEN He. Implementation of Digital Pulse Compression System Based on FPGA[J]. Modern Electronic Technique, 2010, 33(14): 190-192,195 |
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| Authors: | PANG Long CHEN He |
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| Affiliation: | (Radar Technology Research Institute, School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China) |
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| Abstract: | A single-channel high-speed data acquisition and digital pulse compression system is implemented for the wideband radar system with LFM signal. ADS5500 is used for 14 b, 60MSPS data acquisition and FPGA is used for 1024 points digital pulse compression （DPC）. The DPC module is designed using FFT IP core which can be reused in different periods of DPC, respectively performing FFT and IFFT calculation, so that the hardware consumption is saved significantly. The block floating-point data format is used to enhance dynamic range, and diminish truncation or rounding error which affects the output signal to noise ratio. |
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| Keywords: | digital pulse compression FFT block floating point IP core FPGA |
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