Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests |
| |
Authors: | Marwan A. Gharaybeh Michael L. Bushnell Vishwani D. Agrawal |
| |
Affiliation: | (1) Synopsys, Inc., Mountain View, CA, 94043;(2) Dept. of Electrical and Computer Eng., Rutgers University, Piscataway, NJ, 08854;(3) Bell Labs, Murray Hill, NJ 07974 |
| |
Abstract: | We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future. |
| |
Keywords: | delay test digital circuit testing fault models path delay faults test generation |
本文献已被 SpringerLink 等数据库收录! |
|