Layout-Specific Circuit Evaluation in 3-D Integrated Circuits |
| |
Authors: | Syed M. Alam Donald E. Troxel Carl V. Thompson |
| |
Affiliation: | (1) Microsystems Technology Laboratories, MIT, USA |
| |
Abstract: | In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D. |
| |
Keywords: | 3-D integrated circuits layout methodology IC performance comparison FPGA reliability |
本文献已被 SpringerLink 等数据库收录! |
|