A 20-Gb/s 1 : 2 demultiplexer in 0.18-μm CMOS |
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引用本文: | 张长春,王志功,施思,李伟.A 20-Gb/s 1 : 2 demultiplexer in 0.18-μm CMOS[J].半导体学报,2009(5):91-95. |
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作者姓名: | 张长春 王志功 施思 李伟 |
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作者单位: | Institute;RF-&;OE-ICs;Southeast;University; |
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基金项目: | supported by the National High Technology Research and Development Program of China(No.2007AA01Z2a5) |
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摘 要: | A 1 : 2 demultiplexer (DEMUX) has been designed and fabricated in SMIC's standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5-20 Gb/s. The chip size is 875×640μm^2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.
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关 键 词: | CMOS技术 解复用器 Gb 数据传输速率 设计理念 输入缓冲器 电流密度 动态范围 |
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