A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition |
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Affiliation: | 1. Scientific Secretary, ISRO, Bengaluru, India;2. Department of ECE, NIT, Tiruchirappalli, India;3. Avionics Entity, VSSC, Department of Space, Thiruvananthapuram, India |
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Abstract: | In this paper, a low-complex chip to extract the Mel Frequency Cepstral Coefficient for a speech recognition system is presented. The architecture can operate in a continuous-flow manner to process streaming or the stored speech signal at high speed. The frame-overlap Hamming window, DFT and Mel-filter bank computations are deeply integrated to share memory buffers and avoid bit-reversal circuit to reduce area and latency. Moreover, normalised energy consumption and area delay product are reduced by 32%, and speed is increased by 5.2 times compared to prior works. Further, the fixed-point word-length is optimised to minimise the area without affecting the accuracy. |
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Keywords: | Automatic speech recognition MFCC ASIC FPGA Fast fourier transform |
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